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· Work with architect in design definition and implementation
· Develop and maintain design spec and micro-architecture spec
· Verilog/VHDL RTL development and debug
· Work with verification team for test plan/strategy to meet all functional requirements and performance
· Work with timing and physical team for timing closure and meet power and area goals
· B.Tech/M.Tech in Electronics/VLSI Engineering with experience of 2-5 years in FPGA Design
· Strong hands-on experience with Verilog RTL-level design, Synthesis, STA, CDC
· Should be able to work independently once the design requirements are specified
· Knowledge of standard interfaces viz., AXI, AHB, DDR, PCIe, Flash-Memory, I2C/SPI is a plus
· Have experience in Synopsys Design Complier and IC Complier
· Must have good spoken and written communication skills
· Collaborate well in a team
Dracaena Technology
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